DDRC_DYN_SOFT_RESET_CR                  0x0
DDRC_DYN_REFRESH_1_CR                   0x27de
DDRC_DYN_REFRESH_2_CR                   0x30f
DDRC_DYN_POWERDOWN_CR                   0x02
DDRC_DYN_DEBUG_CR                       0x00
DDRC_MODE_CR                            0x00C1
DDRC_ADDR_MAP_BANK_CR                   0x099f
DDRC_ECC_DATA_MASK_CR                   0x0000
DDRC_ADDR_MAP_COL_1_CR                  0x3333
DDRC_ADDR_MAP_COL_2_CR                  0xffff
DDRC_ADDR_MAP_ROW_1_CR                  0x7777
DDRC_ADDR_MAP_ROW_2_CR                  0x0fff
DDRC_INIT_1_CR                          0x0001
DDRC_CKE_RSTN_CYCLES_CR1                0x4242
DDRC_CKE_RSTN_CYCLES_CR2                0x8
DDRC_INIT_MR_CR                         0x33
DDRC_INIT_EMR_CR                        0x20
DDRC_INIT_EMR2_CR                       0x0000
DDRC_INIT_EMR3_CR                       0x0000
DDRC_DRAM_BANK_TIMING_PARAM_CR          0xc0
DDRC_DRAM_RD_WR_LATENCY_CR              0x23
DDRC_DRAM_RD_WR_PRE_CR                  0x235
DDRC_DRAM_MR_TIMING_PARAM_CR            0x64
DDRC_DRAM_RAS_TIMING_CR                 0x108
DDRC_DRAM_RD_WR_TRNARND_TIME_CR         0x178
DDRC_DRAM_T_PD_CR                       0x33
DDRC_DRAM_BANK_ACT_TIMING_CR            0x1947
DDRC_ODT_PARAM_1_CR                     0x10
DDRC_ODT_PARAM_2_CR                     0x0000
DDRC_ADDR_MAP_COL_3_CR                  0x3300
DDRC_DEBUG_CR                           0x3300
DDRC_MODE_REG_RD_WR_CR                  0x0000
DDRC_MODE_REG_DATA_CR                   0x0000
DDRC_PWR_SAVE_1_CR                      0x514
DDRC_PWR_SAVE_2_CR                      0x0000
DDRC_ZQ_LONG_TIME_CR                    0x200
DDRC_ZQ_SHORT_TIME_CR                   0x40
DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_CR1    0x12
DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_CR2    0x2
DDRC_PERF_PARAM_1_CR                    0x4000
DDRC_HPR_QUEUE_PARAM_CR1                0x80f8
DDRC_HPR_QUEUE_PARAM_CR2                0x7
DDRC_LPR_QUEUE_PARAM_CR1                0x80f8
DDRC_LPR_QUEUE_PARAM_CR2                0x7
DDRC_WR_QUEUE_PARAM_CR                  0x200
DDRC_PERF_PARAM_2_CR                    0x1
DDRC_PERF_PARAM_3_CR                    0x0000
DDRC_DFI_RDDATA_EN_CR                   0x3
DDRC_DFI_MIN_CTRLUPD_TIMING_CR          0x0003
DDRC_DFI_MAX_CTRLUPD_TIMING_CR          0x0040
DDRC_DFI_WR_LVL_CONTROL_CR1             0x0000
DDRC_DFI_WR_LVL_CONTROL_CR2             0x0000
DDRC_DFI_RD_LVL_CONTROL_CR1             0x0000
DDRC_DFI_RD_LVL_CONTROL_CR2             0x0000
DDRC_DFI_CTRLUPD_TIME_INTERVAL_CR       0x309
DDRC_DYN_SOFT_RESET_ALIAS_CR            0x4
DDRC_AXI_FABRIC_PRI_ID_CR               0x0000
DDRC_ECC_INT_CLR_REG                    0x0000
PHY_DYN_BIST_TEST_CR                    0x0
PHY_DYN_BIST_TEST_ERRCLR_CR1            0x0
PHY_DYN_BIST_TEST_ERRCLR_CR2            0x0
PHY_DYN_BIST_TEST_ERRCLR_CR3            0x0
PHY_BIST_TEST_SHIFT_PATTERN_CR1         0x0
PHY_BIST_TEST_SHIFT_PATTERN_CR2         0x0
PHY_BIST_TEST_SHIFT_PATTERN_CR3         0x0
PHY_LOOPBACK_TEST_CR                    0x0000
PHY_BOARD_LOOPBACK_CR                   0x0
PHY_CTRL_SLAVE_RATIO_CR                 0x80
PHY_CTRL_SLAVE_FORCE_CR                 0x0
PHY_CTRL_SLAVE_DELAY_CR                 0x0
PHY_DATA_SLICE_IN_USE_CR                0x3
PHY_LVL_NUM_OF_DQ0_CR                   0x0
PHY_DQ_OFFSET_CR1                       0x0
PHY_DQ_OFFSET_CR2                       0x0
PHY_DQ_OFFSET_CR3                       0x0
PHY_DIS_CALIB_RST_CR                    0x0
PHY_DLL_LOCK_DIFF_CR                    0xb
PHY_FIFO_WE_IN_DELAY_CR1                0x0
PHY_FIFO_WE_IN_DELAY_CR2                0x0
PHY_FIFO_WE_IN_DELAY_CR3                0x0
PHY_FIFO_WE_IN_FORCE_CR                 0x0
PHY_FIFO_WE_SLAVE_RATIO_CR1             0x40
PHY_FIFO_WE_SLAVE_RATIO_CR2             0x401
PHY_FIFO_WE_SLAVE_RATIO_CR3             0x4010
PHY_FIFO_WE_SLAVE_RATIO_CR4             0x0
PHY_GATELVL_INIT_MODE_CR                0x0
PHY_GATELVL_INIT_RATIO_CR1              0x0
PHY_GATELVL_INIT_RATIO_CR2              0x0
PHY_GATELVL_INIT_RATIO_CR3              0x0
PHY_GATELVL_INIT_RATIO_CR4              0x0
PHY_LOCAL_ODT_CR                        0x1
PHY_INVERT_CLKOUT_CR                    0x0
PHY_RD_DQS_SLAVE_DELAY_CR1              0x0
PHY_RD_DQS_SLAVE_DELAY_CR2              0x0
PHY_RD_DQS_SLAVE_DELAY_CR3              0x0
PHY_RD_DQS_SLAVE_FORCE_CR               0x0
PHY_RD_DQS_SLAVE_RATIO_CR1              0x40
PHY_RD_DQS_SLAVE_RATIO_CR2              0x401
PHY_RD_DQS_SLAVE_RATIO_CR3              0x4010
PHY_RD_DQS_SLAVE_RATIO_CR4              0x0
PHY_WR_DQS_SLAVE_DELAY_CR1              0x0
PHY_WR_DQS_SLAVE_DELAY_CR2              0x0
PHY_WR_DQS_SLAVE_DELAY_CR3              0x0
PHY_WR_DQS_SLAVE_FORCE_CR               0x0
PHY_WR_DQS_SLAVE_RATIO_CR1              0x0
PHY_WR_DQS_SLAVE_RATIO_CR2              0x0
PHY_WR_DQS_SLAVE_RATIO_CR3              0x0
PHY_WR_DQS_SLAVE_RATIO_CR4              0x0
PHY_WR_DATA_SLAVE_DELAY_CR1             0x0
PHY_WR_DATA_SLAVE_DELAY_CR2             0x0
PHY_WR_DATA_SLAVE_DELAY_CR3             0x0
PHY_WR_DATA_SLAVE_FORCE_CR              0x0
PHY_WR_DATA_SLAVE_RATIO_CR1             0x40
PHY_WR_DATA_SLAVE_RATIO_CR2             0x401
PHY_WR_DATA_SLAVE_RATIO_CR3             0x4010
PHY_WR_DATA_SLAVE_RATIO_CR4             0x0
PHY_WRLVL_INIT_MODE_CR                  0x0
PHY_WRLVL_INIT_RATIO_CR1                0x0
PHY_WRLVL_INIT_RATIO_CR2                0x0
PHY_WRLVL_INIT_RATIO_CR3                0x0
PHY_WRLVL_INIT_RATIO_CR4                0x0
PHY_WR_RD_RL_CR                         0x21
PHY_RDC_FIFO_RST_ERR_CNT_CLR_CR         0x0
PHY_RDC_WE_TO_RE_DELAY_CR               0x3
PHY_USE_FIXED_RE_CR                     0x1
PHY_USE_RANK0_DELAYS_CR                 0x1
PHY_USE_LVL_TRNG_LEVEL_CR               0x0
PHY_DYN_CONFIG_CR                       0x0009
PHY_RD_WR_GATE_LVL_CR                   0x0
PHY_DYN_RESET_CR                        0x1
DDR_FIC_NB_ADDR_CR                      0x0
DDR_FIC_NBRWB_SIZE_CR                   0x0
DDR_FIC_WB_TIMEOUT_CR                   0x0
DDR_FIC_HPD_SW_RW_EN_CR                 0x0
DDR_FIC_HPD_SW_RW_INVAL_CR              0x0
DDR_FIC_SW_WR_ERCLR_CR                  0x0
DDR_FIC_ERR_INT_ENABLE_CR               0x0
DDR_FIC_NUM_AHB_MASTERS_CR              0x0
DDR_FIC_LOCK_TIMEOUTVAL_CR1             0x0
DDR_FIC_LOCK_TIMEOUTVAL_CR2             0x0
DDR_FIC_LOCK_TIMEOUT_EN_CR              0x0
